4. Assembly Language & Computer Architecture

The speaker details the four stages of compilation: preprocessing, compiling, assembling, and linking. Clang is used as an example compiler. Preprocessing handles macros, compiling produces assembly code, assembling creates object files, and linking combines these into a final executable.

Assembly is presented as a human-readable mnemonic representation of machine code. The process of generating assembly code (clang minus s) and disassembling machine code back to assembly (objdump) is explained, highlighting the close relationship between assembly and machine code.

Several reasons for studying assembly are provided: it reveals compiler optimizations or lack thereof, helps identify compiler bugs, allows writing hand-optimized code when compilers fail, and enables reverse engineering software without source code.

Students are expected to understand how compilers implement C constructs with x86 instructions, read x86 assembly with an architecture manual, grasp performance implications of common assembly patterns, and potentially write assembly using compiler intrinsics.

The core concepts of the x86-64 ISA are introduced: registers, instructions, data types, and memory addressing modes. The lecture aims to provide a deeper understanding beyond immediate practical needs.

A detailed explanation of x86 registers, including general-purpose registers, the RFLAGS register, the instruction pointer, and vector registers (SSE and AVX). The historical evolution from 16-bit to 64-bit architecture is discussed, explaining aliases and naming conventions.

The standard format for x86-64 instructions (opcode and operand list) is introduced. The difference between AT&T and Intel syntax for operand order is highlighted. A list of common opcodes like MOVE, ADD, SUB, conditional moves, and logical operations is presented.

Opcodes can be augmented with suffixes to denote data types (e.g., 'q' for quad word) or condition codes. The historical context of data type naming (e.g., quad word meaning 8 bytes) is explained. Sign extension using 'z' for zero-extend and 's' for sign-extend is also covered.

Conditional jumps and moves use suffixes related to condition codes, which are set in the RFLAGS register by previous operations. Examples like 'ne' (not equal) and status flags like Carry, Zero, Sign, and Overflow are discussed. An idiom for checking if a register is zero is shown.

Both direct (immediate, register, direct memory) and indirect (register indirect, register indexed, instruction-pointer relative, base indexed scale displacement) addressing modes are explained. The performance implications of accessing memory vs. registers are emphasized, introducing the concept of caching.

Common assembly idioms, such as XORing a register with itself to zero it and using 'test' to check for zero, are discussed. The generation of NOP (no operation) instructions by compilers for alignment and code size optimization is also presented.

The history and current state of floating-point operations are covered, distinguishing between scalar floating-point (SSE and x87 instructions) and vector operations (SSE, AVX, AVX2, AVX-512). The structure and operation of vector units, including parallelism across lanes, are detailed.

An overview of modern computer architecture is given, starting with the traditional 5-stage pipeline and then comparing it to complex processors like the Intel Haswell, which has many more pipeline stages. The focus shifts to exploiting parallelism and locality in processor design.

The concept of instruction-level parallelism (ILP) is explored, aiming to execute multiple instructions simultaneously. Pipeline stalls due to hazards (structural, data, and control) are explained. Data hazards, including true dependence, anti-dependence, and output dependence, are discussed in detail.

The varying latencies of different operations (e.g., integer division, multiply, fused multiply-add) are presented. The strategy of using separate functional units for complex operations and the concept of superscalar processors, which fetch and issue multiple instructions per cycle, are introduced.

Techniques to overcome pipeline stalls, such as bypassing (feeding results directly to subsequent instructions), register renaming, and out-of-order execution, are briefly mentioned. The lecture concludes with an explanation of branch prediction and the costs of mispredicted branches in speculative execution.

The lecture introduces the importance of understanding assembly language and computer architecture for writing fast code, explaining that it allows exploitation of architectural strengths. It contrasts the insulation of modern software development from performance concerns with the need to understand the underlying hardware.