Summary
Highlights
The lecture begins by introducing the concept of a stored program, emphasizing that this wasn't always the case for early computers like ENIAC, where programming involved manually connecting wires. This inefficient method highlighted the need for a better programming model, leading to the stored program concept.
John von Neumann's model is presented as a solution, proposing to store programs in memory alongside data. This model defines principles for computer design, including simplicity, linearity, sequentiality, and centrality. A key characteristic is the 'unicidade' (oneness) of memory, where both data and instructions share the same space.
The Von Neumann model's architecture consists of memory, input/output devices, and a processor divided into a control unit and an arithmetic logic unit (ALU). The control unit fetches instructions, and the ALU fetches data from the same memory. The process of instruction execution involves a continuous loop of fetching, decoding, and executing instructions, with results typically stored in an accumulator.
In contrast to Von Neumann, the Harvard architecture is introduced, distinguishing itself by having separate memories and buses for instructions and data. This separation aims to overcome the bottleneck of a single bus access in the Von Neumann model, potentially offering better performance in certain applications.
The lecture discusses how Von Neumann and Harvard architectures are applied in modern computing. Embedded systems and microcontrollers typically use the Harvard architecture due to their fixed tasks, while modern desktop processors (ARM, Intel) combine aspects of both, often separating instruction and data caches at the first memory level while maintaining a unified main memory.
Four main CPU organization models are detailed: stack-based, accumulator-based (as in Von Neumann), memory-memory, and register-register. Each model dictates how operands are accessed and processed by the ALU, influencing flexibility, speed, and the number of instructions required for operations.
A simple 'C = A + B' instruction is used to demonstrate how each CPU organization model executes, highlighting the varying number of instructions and execution characteristics. The discussion emphasizes that fewer instructions do not always equate to faster execution, as cycle time and data flow characteristics also play a crucial role in overall performance.