Summary
Highlights
Semiconductor packaging involves a series of steps to transform individual silicon chips from a wafer into a molded device ready for use in electronic systems. This process protects the delicate chips from damage and environmental factors.
The fundamental steps include wafer saw (cutting wafers into chips), die attach (mounting chips onto lead frames), wire bonding (connecting chip terminals to lead frames), molding (encapsulating the device), marking (adding device information), plating, trim and form, singulation, and final testing.
Wafer saw is the delicate process of cutting brittle wafers into individual chips. Wafers come in various sizes (4, 5, 6, 8, and 12-inch diameters), with larger wafers (12-inch) used for advanced, high-pin-count ICs, requiring more advanced equipment due to their fragility.
Before sawing, wafers are mounted on a tape attached to a metal ring, ensuring stability during and after the cutting process. Sawing uses diamond blades to cut along saw streets, avoiding damage to the active circuit. Proper wafer orientation and bubble-free mounting are critical to prevent defects like misaligned cuts or die fly-offs.
Die attach is the process of mounting the die onto a lead frame or substrate, typically using silver-filled adhesive epoxy for ICs or soft solder/eutectic methods for diodes and transistors. Lead frames (copper alloy) and laminate substrates (for BGA packages) are common mounting materials, chosen based on cost and device requirements.
A full die attach process involves precise, high-tech machines. Lead frames are loaded, epoxy is dispensed, and dies are picked from the wafer and placed onto the lead frame. Only known good dies (KGD), identified by wafer maps (representing good dies with '1' and bad dies with '0'), are processed to avoid waste.
Key specifications for die attach include 100% epoxy coverage under the die, visible epoxy fillet (>90% on each side), and controlled bond line thickness (BLT) of at least 25µm. Proper dispensing nozzles are chosen based on die size, and ejector needle configurations prevent damage to the die. Defects like epoxy voids or manifestations on the die surface are considered rejects.
Wire bonding is a complex interconnect process that connects die bond pads to lead frame leads. Gold wire is common due to excellent conductivity and malleability, though denser copper wire is becoming popular due to cost, despite being harder to bond and susceptible to oxidation. Aluminum wire is used for power devices, allowing larger diameters for higher current.
The bonding cycle starts with a free air ball on the capillary tip. It descends to the bond pad, applies force and ultrasonic power to form the 'first bond.' The capillary then moves up, forming a wire loop, and then moves to the lead to create the 'second bond' or stitch. A high-voltage spark creates a new free air ball for the next cycle.
Bond pad composition (aluminum with impurities) and dimensions (bond pad opening/BPO, bond pad pitch/BPP) are critical for effective bonding. Capillary selection factors in chamfer diameter (CD) and chamfer angle (CA) for first bond formation, and face angle (FA) and outer radius (OR) for stitch formation. Capillary life is generally one million bonds before gold buildup affects quality.
Setting up wire bonding involves understanding device details (bond pad dimensions, layout, die thickness) and selecting the correct capillary type (standard or bottleneck). Machine calibration (XY table, bond head) and temperature control (heater block) are crucial for precision and consistency. Capillary-to-camera offset must be aligned to ensure accurate bond placement, and bonding trials are conducted to optimize parameters.
Visual inspection under a microscope is essential for assessing bond quality. Common defects include non-stick on pad (NSOP), lifted balls (weak first bond), smashed balls (over-bonding), golf club balls (improper free air ball formation), bond craters (pad damage), oversized balls, and weak stitches. Bond strength is verified through destructive tests like bond shear and wire pull.
To accommodate thinner packages and more complex designs, advanced techniques like reverse bonding are used. Reverse bonding places the first bond on the lead/substrate and the second bond on the die, improving stability and allowing for higher kink height. Ball Stitch On Ball (BSOB) or Stand Off Stitch Bonding (SSB) further enhances this by bonding a bump on the die pad, protecting the die from impact.
After interconnect, semiconductor devices are encapsulated using molding processes to protect them from damage and the environment. Transfer molding is common for leadframe-based and BGA packages, using preheated thermoset pellets pressed into cavities. Compression molding is used for advanced packaging (e.g., panel/wafer level) where minimal material flow is needed to protect delicate internal structures.
Ball Grid Array (BGA) packages are popular for advanced ICs, offering high interconnect density and reduced board space compared to QFP. Variations include Plastic BGA (PBGA), typically wire-bonded, and Fine Pitch BGA (FBGA) for higher pin counts. Flip-Chip BGA further optimizes performance and thermal management by directly attaching a heatsink to the exposed die backside.
BGA package performance relies on robust substrate materials and designs, adhering to IPC standards like IPC 6011 (performance classes), IPC 6012 (rigid printed boards), and IPC 2226 (HDI requirements). Substrates consist of a core material with copper foil and built-up layers of prepreg, interconnected by vias. Coreless substrates offer thinner profiles but are more prone to warpage.
For wire-bonded BGA, the process includes wafer backgrind and sawing, followed by die attach onto the laminate substrate. Plasma cleaning prepares the device for fine-pitch, low-loop, and long-wire wire bonding. After bonding, the device undergoes another plasma clean before molding. Subsequent steps involve laser marking, ball attach, singulation, and 100% electrical testing.
Flip-chip BGA assembly starts with a bumping process where die bond pads are redistributed for flip-chip configuration. After backgrinding and sawing, bumped dies are transferred to carriers. A high-speed flip-chip bonder applies solder paste to substrate pads, followed by reflow soldering and cleaning. Underfill epoxy fills gaps between the die and substrate, providing mechanical support. The package is then encapsulated (molded or with a metal lid), followed by ball mount, singulation, and electrical testing.
Flip-chip technology offers shorter connections, improved electrical performance, and smaller footprints. It requires Redistribution Layers (RDL) to reroute bond pads and Under Bump Metallization (UBM) for bump attachment. Flip-chip reliability is ensured by filling gaps between the chip and PCB with underfill epoxy, which reduces thermal mismatch and mechanically stabilizes the die and solder bumps. Plasma cleaning is crucial for proper underfill flow.
Flip-chip is integral to BGA packaging, allowing high I/O density and improved thermal performance with direct heatsink contact. Lidless BGA is suitable for smaller, low-power applications, while lidded flip-chip BGA offers enhanced thermal management and signal integrity. Flip-chip is also key to multi-chip modules and chiplets, enabling several ICs to be integrated on a single substrate for complex systems.