Summary
Highlights
This multi-part video series provides a thorough introduction to RISC-V Assembly Language programming, starting with the processor architecture, registers, and detailed instruction descriptions. The initial videos are for beginners, while later videos will cover advanced topics like trap handling, virtual memory, and optional extensions for experienced programmers.
Machine code is the binary, executable instructions stored in a computer's memory, directly processed by hardware. Assembly code is a human-readable representation of these instructions, ideally with a one-to-one correspondence. Each architecture has its own machine code and assembly language; this series focuses on RISC-V.
RISC-V processors feature 32 general-purpose registers. There are two main variants: RV32 (32-bit registers) and RV64 (64-bit registers). These registers are general-purpose, meaning any instruction requiring a register can use any of them, with one exception. There are also a program counter (PC) and control and status registers (CSRs).
Standard data sizes in RISC-V include a byte (8 bits), half word (16 bits), word (32 bits), and double word (64 bits). The size of a register depends on the RISC-V variant: RV32 registers hold a word (4 bytes), while RV64 registers hold a double word (8 bytes). Data can represent integers (signed or unsigned), characters, or bit strings.
Integers can be represented as signed or unsigned. Signed representation splits the range between positive and negative numbers, while unsigned representation eliminates negative numbers, effectively doubling the positive range. For larger data types like double words (64-bit), signed representation offers a vast range, making unsigned representation rarely necessary for general integer values, though it's still used for addresses and pointers.
RISC-V has two instruction sets. The mandatory full-sized instruction set consists of 32-bit instructions, regardless of the processor's register size. The optional compressed instruction set uses 16-bit instructions, serving as shorthand for common full-sized instructions, increasing execution speed. Compressed instructions start with 'C.' and a period.
The program counter (PC) is not a general-purpose register; it holds the address of the next instruction to execute. Its size matches the general-purpose registers (32 bits for RV32, 64 bits for RV64), though it might be smaller if memory addressing doesn't require all bits. The PC increments as instructions are executed to fetch subsequent instructions from memory.
RISC-V assembly instructions consist of an opcode (e.g., 'add'), operands (registers or values), and optional comments. Each instruction resides on a separate line, and an optional label can precede it, providing a symbolic name to the instruction's memory address. Labels are identified by a colon. Operands are contained by brackets to indicate they're optional.
The 32 general-purpose registers (x0 through x31) also have alternate, more descriptive names (e.g., zero, ra, sp, gp, tp, t0-t6, s0-s11, a0-a7). Programmers are encouraged to use these alternate names for better readability and understanding of register functions.
Register x0, or 'zero', is unique as it's hardwired to always contain the value zero. It can be used as a source for the value zero or as a destination register when the instruction result is to be discarded. This is the only register that is not general-purpose in its functionality.
The return address register (ra), or x1, stores the return address for function calls. Unlike some architectures, RISC-V call instructions don't push the return address onto an in-memory stack, but rather save it in 'ra'. This makes calls and returns faster as they avoid memory access. However, for nested calls, the programmer must manually save and restore 'ra' from the stack. Leaf functions (those that don't call other functions) can leverage this for very quick calls.
The stack pointer register (sp), or x2, is used by convention to point to an in-memory stack. RISC-V does not have a dedicated hardware stack pointer, so any general-purpose register could technically be used, but convention dictates x2. While full instruction sets treat it as a general-purpose register, some compressed instructions implicitly assume x2 for stack operations.
Registers a0 through a7 (x10-x17) are conventionally used to pass up to eight arguments to functions. If more arguments are needed or arguments are larger than register size, they must be passed on the stack. Function return values are conventionally placed in register a0.
Registers t0 through t6 (x5-x7, x28-x31) are temporary work registers. They are 'caller-saved', meaning if a function calls another sub-function, and the caller wants to preserve the values in these registers, it is the caller's responsibility to save and restore them (e.g., to the stack), as the called function might modify them.
Registers s0 through s11 (x8-x9, x18-x27) are also general work registers, but they are 'callee-saved'. This means if a function uses these registers, it must save their original values before use and restore them before returning, ensuring their preservation across function calls. Callers can rely on these registers maintaining their values after a function call.
The global pointer (gp), or x3, points to an area for global or static variables, simplifying their addressing. The thread pointer (tp), or x4, points to an area for thread-specific variables, such as thread identifiers or local global variables, also facilitating easier addressing. These registers might not be used frequently by every programmer but are part of the complete architecture.