Summary
Highlights
The lecture begins by drawing parallels between real-world architecture, specifically Frank Lloyd Wright's Fallingwater, and computer architecture. It emphasizes the importance of creative thinking, understanding trade-offs, and principled design, similar to Wright's organic architecture philosophy. Students are encouraged to visit Fallingwater and reflect on design principles. The discussion highlights the differences between traditional and innovative designs, stressing that good design is context-dependent and involves considering factors like cost and purpose.
The lecturer outlines the multifaceted role of a computer architect, which involves looking backward to learn from past designs, looking forward to envision future innovations, and looking up and down the abstraction hierarchy. Architects must understand foundational problems (like genomics for medicine) and the underlying circuit and device technologies. This comprehensive view is crucial for designing systems that can adapt to future workloads and technological advancements, emphasizing that computer architecture is both a science and an art requiring intuition and insight.
Richard Hamming's quote, 'The purpose of computing is insight,' frames the discussion on the layers of abstraction in computing, from high-level problems to low-level electrons. Various interfaces—algorithms, programming languages, operating systems, instruction set architectures (ISA), microarchitecture, logic gates, circuits, and physics—are introduced. Abstraction is beneficial for productivity, as programmers don't need to understand every underlying detail. However, understanding these layers is critical for debugging, optimizing, and developing efficient and innovative systems. The concept of Hamming distance is briefly explained as an example of a foundational concept in computing.
The lecture presents a practical problem: two applications (MATLAB and GCC) running on a multi-core system experience disproportionate slowdowns. This is attributed to the DRAM memory controller's unfair scheduling policy, which prioritizes row hits to maximize throughput, inadvertently penalizing applications with random access patterns. The internal operation of a DRAM bank, including row buffers and the long latency of row conflicts, is explained. This example illustrates how a design choice at one abstraction layer (memory controller design) can have significant, unintended consequences at higher layers (application performance and fairness).
Solutions to the DRAM fairness problem are discussed, focusing on where in the abstraction hierarchy the problem can be best addressed. While system software or even the programmer could attempt solutions, the memory controller itself is identified as an effective point due to its visibility into all request streams. Potential solutions include designing memory controllers to be fair to different applications or using system software to map applications to different DRAM channels to avoid interference. This problem underscores the course's goal of enabling students to make design decisions that cross different layers and system components.
Another modern challenge, DRAM refresh, is introduced. DRAM cells leak charge, requiring periodic refreshing, which consumes significant energy and degrades performance. As DRAM capacity increases, the percentage of time and energy spent on refreshing becomes unsustainable (e.g., 46% of throughput and 50% of energy for a future 64 GB chip). The underlying cause is manufacturing process variation, leading to a wide distribution of retention times among DRAM cells, but current systems refresh all cells uniformly at the lowest common denominator.
Solutions to the DRAM refresh problem involve exposing retention time information across abstraction layers. By profiling each row's actual retention time and storing this information (e.g., in the memory controller using a Bloom filter), refresh operations can be varied. Weak cells are refreshed more frequently, strong cells less so. This approach can reduce refresh operations by up to 75%, leading to significant power reduction and performance improvement. This again highlights the power of breaking abstraction barriers for more effective system design.
The 'Row Hammer' problem is introduced: repeatedly activating and pre-charging a DRAM row (the 'aggressor' row) can cause bit flips in physically adjacent rows (the 'victim' rows). This is a circuit-level disturbance effect exacerbated by aggressive DRAM scaling. It represents a significant reliability and security vulnerability in modern systems. Experimental evidence shows that over 80% of current DRAM chips are susceptible. Solutions range from improving manufacturing processes, using stronger error-correcting codes, or making DRAM controllers more intelligent to proactively fix errors (e.g., probabilistically refreshing adjacent rows).
The lecture concludes by reiterating the course goals: understanding how computing platforms work, implementing simple platforms, analyzing design decisions' impact, thinking critically and broadly across abstraction levels, and making informed trade-offs. Logistical details are provided, including professor and TA introductions, communication channels (Piazza, email), course website resources, attendance recommendations, recitation sessions, and academic integrity policies. The grading scheme, homework assignments (including a mandatory 'Homework Zero' and initial reading summaries), and lab expectations (eight labs, starting with a MIPS simulator) are also outlined.